Vertical Research Group

Overview

The research in the Vertical group spans VLSI technology to software and application analysis. Such an integrated approach is necessary to design future high performance systems. Our research focuses on future systems targeting a 2020 time-frame.

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1.  Reliability Aware Systems (REAL)

Technology constraints and application characteristics are radically changing as we scale to the end of silicon technology and transition to post-CMOS devices. Devices are becoming increasingly brittle, highly varying in their properties, and error-prone, leading to a fundamentally unpredictable hardware substrate. The model of hardware being correct all the time, on all regions of chip, and forever, becomes prohibitively expensive to maintain. Emerging new classes of applications are increasingly relying on probabilistic methods. They have an inherent tolerance for uncertainty, do not require hardware to be correct all the time, and this provides an opportunity to creatively utilize hardware.

We are investigating Reliability Aware Systems (REAL) in which, we expose device properties through layers of the system stack up to the application. This is a radical departure from conventional systems that attempt to hide and mask unpredictable behavior to create an illusion of perfection. We are building system software, architecture, and microarchitectural mechanisms that can scale to future technologies.

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2.  Copernicus: Multicore Ray-Tracing

Providing significant improvement to visual quality for 3D graphics requires a fundamentally new system-level rethink from algorithms down to the architecture. The conventional Z-buffer algorithm and the architecture model of GPUs does not provide sufficient support for complex illumination effects like soft-shadows, reflections, and defocus blurring for example. In this project, we target the entire graphics system stack and are developing algorithms and software architecture, hardware architecture, and analysis tools to build next-generation 3D graphics systems for real-time ray tracing. The end goal of this project is to build this protoype chip and run real games and real workload at real-time rates.

CopernicusPublic?

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3.  PLUG: Lookup modules for network processors

High-end routers and switches perform performance-critical lookups into large data based on network packet content. Current designs rely on specialized hardware modules for high performance. While mostly sufficient, emerging new protocols create a problem. For them to be deployed, expensive equipment upgrades are required for each protocol. To support the rapid deployment of new data plane protocols, we are investigating the PLUG system which includes a programming model, compiler, and architecture. This project seeks to develop a unified framework for future network devices with four components: a) an abstract execution model to represent hardware, b) a toolchain to ease implementation, d) quantitative performance evaluation of protocols, and d) programmable hardware architectures specialized for the core operations in network protocols.

Project homepage

4.  Other Projects

4.1  Mapreduce for Cell

We have developed a MapReduce runtime for the Cell processor. A tech report describes more about this work. The project is hosted on sourceforge. MapReduce for Cell on Sourceforge. More details in our Tools page

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