- Computer Sciences
Guri Sohi received a Ph.D in electrical and computer engineering from the University of Illinois. He has been a faculty member at the University of Wisconsin-Madison since 1985. He is currently the John P. Morgridge Professor and the E. David Cronon Professor of Computer Sciences in the Department of Computer Sciences and Department of Electrical and Computer Engineering. He served as chair of the computer sciences department from 2004 through 2008, and began a second term as chair on July 1, 2017. In 2015, he was named a Vilas Research Professor.
Sohi's research has been in the design of high-performance computer systems. He has co-authored several papers and patents that have influenced both researchers and commercial microprocessors. In the mid 1980s, while most computer architects were investigating in-order processors, he investigated out-of-order processors. His paper "Instruction Issue Logic for High-Performance, Interruptible Pipelined Processors" (in ISCA 1987) articulated a model for a dynamically-scheduled processor supporting precise exceptions, a model that was widely adopted by several microprocessor manufacturers. (This paper, and the journal version in IEEE Trans. on Computers, March 1990, have been referenced by over 150 U.S. patents.) His paper "High Bandwidth Data Memory Systems for Superscalar Processors" (in ASPLOS 1991) argued for non-blocking (or lockup-free) caches, and it was instrumental in influencing high-end microprocessors to switch from blocking to non-blocking caches. In the early 1990s, while other computer architects started investigating out-of-order processors he proposed the concept of multiscalar processors and thread-level speculation in his papers "The Expandable Split Window Paradigm for Exploiting Fine-Grain Parallelism" (in ISCA 1992) and "Multiscalar Processors" (in ISCA 1995). Thread-level speculation and its variants are currently one of the most active areas of research in computer architecture. His paper "Dynamic Speculation and Synchronization of Data Dependences" (in ISCA 1997) introduced the idea of memory dependence prediction, an idea that was used in the Alpha processor designs and is being considered by others. His paper "Dynamic Instruction Reuse" (in ISCA 1997) proposed the concept of instruction reuse, another area of active research. He and his students also had the first academic proposal for trace caches. Sohi's research group also developed the Simplescalar simulator, a simulation toolset that is widely used for research and instruction.
Sohi has interacted heavily with industry. Over the years, he has discussed his research with architects and given talks in design groups at most of the leading microprocessor manufacturers, including Digital Equipment, HaL, Hewlett-Packard, IBM, Intel, MIPS, Motorola, Silicon Graphics and Sun Microsystems.