Wisconsin Multifacet Project

By Year: 2009, 2008, 2007, 2006, 2005, 2004, 2003, 2002, 2001, 2000, 1999, 1998

By Topic:

• Transactional Memory (see also LogTM Home Page)
• Multiprocessor Design, Specification, & Verification
• Availability
• Deterministic Recording & Replay
• Workload Analysis & Improvement
• Modeling & Simulation
• Miscellaneous

Transactional Memory

• StealthTest: Low Overhead Online Software Testing using Transactional Memory,
  Jayaram Bobba, Weiwei Xiong, Luke Yen, Mark D. Hill, and David A. Wood
  Conference on Parallel Architectures and Compilation Techniques (PACT), Sep 2009.
  Paper: pdf
  Talk: ppt
  

• xCalls: Safe I/O in Memory Transactions,
  Haris Volos, Andres Jaan Tack,Neelam Goyal, Michael M. Swift, Adam Welc
  4th ACM european conference on Computer systems (EuroSys), April 2009
  Paper: pdf
  Talk: ppt

• Condition Variables and Transactional Memory: Problem or Opportunity?,
  Polina Dudnik and Michael M. Swift
  4th ACM SIGPLAN Workshop on Transactional Computing (TRANSACT), February 2009.
  Paper: pdf
  Talk: ppt

• Notary: Hardware Techniques to Enhance Signatures,
  Luke Yen, Stark C. Draper, and Mark D. Hill
  41st International Symposium on Microarchitecture (MICRO), November 2008.
  Paper: pdf
  Talk: ppt

• Is Transactional Memory an Oxymoron?,
  Mark D. Hill
  Very Large Data Bases (VLDB) August 2008.
  Keynote Talk: ppt
  

• TokenTM: Efficient Execution of Large Transactions with Hardware Transactional Memory,
  Jayaram Bobba, Neelam Goyal, Mark D. Hill, Michael M. Swift, and David A. Wood
  International Symposium on Computer Architecture (ISCA), June 2008.
  Paper: pdf
  Talk: ppt
  

• OS Support for Virtualizing Transactional Memory,
  Michael M. Swift, Haris Volos, Neelam Goyal, Luke Yen, Mark D. Hill and David A Wood
  Third ACM SIGPLAN Workshop on Transactional Memory (TRANSACT), February 2008.
  Also appears as Univ. of Wisconsin Computer Sciences Technical Report CS-TR-2008-1630, February 2008.
  Paper: pdf
  Talk: ppt

• Pathological Interaction of Locks with Transactional Memory,
  Haris Volos, Neelam Goyal and Michael M. Swift
  Third ACM SIGPLAN Workshop on Transactional Memory (TRANSACT), February 2008.
  Also appears as Univ. of Wisconsin Computer Sciences Technical Report CS-TR-2008-1631, February 2008.
  Paper: pdf
  Talk: ppt
  

• Implementing Signatures for Transactional Memory,
  Daniel Sanchez, Luke Yen, Mark D. Hill, and Karthikeyan Sankaralingam
  40th International Symposium on Microarchitecture (MICRO), December 2007.
  Paper: pdf
  Talk: ppt
  

• Design and Implementation of Signatures for Transactional Memory Systems,
  Daniel Sanchez,
  Univ. of Wisconsin Computer Sciences Technical Report CS-TR-2007-1611, September 2007.
  Technical Report: pdf
  Talk: ppt

• A Case for Deconstructing Hardware Transactional Memory Systems,
  Mark D. Hill, Derek Hower, Kevin E. Moore, Michael M. Swift, Haris Volos and David A. Wood
  Univ. of Wisconsin Computer Sciences Technical Report CS-TR-2007-1594, June 2007.
  Technical Report: pdf
  Also appears as Dagstuhl Seminar Proceedings 07361, editors Albert Cohen, Maria J. Garzaran, Christian Lengauer, and Samuel P. Midkiff, 2008.
  Report: pdf

• Performance Pathologies in Hardware Transactional Memory,
  Jayaram Bobba, Kevin E. Moore, Haris Volos, Luke Yen, Mark D. Hill, Michael M. Swift, and David A. Wood
  International Symposium on Computer Architecture (ISCA), June 2007.
  (Shorter, award version appears in Micro Top Picks Jan/Feb 2008)
  Paper: pdf
  Reference: ACM
  Talk: ppt Extended Talk: ppt
  

• Log-based Transactional Memory,
  Overview Talk, April 2007.
  

• LogTM-SE: Decoupling Hardware Transactional Memory from Caches,
  Luke Yen, Jayaram Bobba, Michael R. Marty, Kevin E. Moore, Haris Volos, Mark D. Hill, Michael M. Swift, and David A. Wood
  International Symposium on High Performance Computer Architecture (HPCA), February 2007.
  Paper: pdf
  Reference: IEEE Xplore
  Talk: ppt, pdf

• Supporting Nested Transactional Memory in LogTM,
  Michelle J. Moravan, Jayaram Bobba, Kevin E. Moore, Luke Yen, Mark D. Hill, Ben Liblit, Michael M. Swift and David A. Wood
  International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October 2006.
  Paper: pdf
  Reference: ACM
  Talk: pdf, ppt

• An Operational Semantics for LogTM,
  Ben Liblit,
  Univ. of Wisconsin Computer Sciences Technical Report CS-TR-2006-1571, August 2006.
  Technical Report: pdf

• LogTM: Log-based Transactional Memory,
  Kevin E. Moore, Jayaram Bobba, Michelle J. Moravan, Mark D. Hill and David A. Wood
  International Symposium on High Performance Computer Architecture (HPCA), February 2006.
  Paper: pdf
  Reference: IEEE Xplore
  Talk: ppt, pdf
  

• Thread-Level Transactional Memory,
  Kevin E. Moore, Mark D. Hill, and David A. Wood,
  Univ. of Wisconsin Computer Sciences Technical Report CS-TR-2005-1524, March 2005.
  Technical Report: pdf

• Thread-Level Transactional Memory,
  Kevin E. Moore
  Wisconsin Industrial Affiliates Meeting, October 2004.
  Talk: pdf, ppt
  

Multiprocessor Design, Specification, & Verification

• Amdahl's Law in the Multicore Era,
  Mark D. Hill and Michael R. Marty,
  IEEE Computer, July 2008.
  Paper: pdf
  Supplementary Website: http://www.cs.wisc.edu/multifacet/amdahl/
  YouTube Video (52 minutes): Google TechTalk 02/2009
  Related Talks: HPCA Keynote 02/2008 and Colloquium 08/2008
  Original Technical Report (UW CS-TR-2007-1593, April 2007): pdf

• Virtual Hierarchies,
  Michael R. Marty and Mark D. Hill,
  IEEE Micro Special Issue: Micro's Top Picks from Microarchitecture Conferences, January-February 2008.
  (Shorter, award version of ISCA2007 Paper)
  Paper: pdf
  

• Virtual Hierarchies to Support Server Consolidation,
  Michael R. Marty and Mark D. Hill
  International Symposium on Computer Architecture (ISCA), June 2007.
  (Shorter, award version appears in Micro Top Picks Jan/Feb 2008)
  Paper: pdf
  Talk: ppt
  

• Interactions Between Compression and Prefetching in Chip Multiprocessors,
  Alaa R. Alameldeen and David A. Wood
  International Symposium on High Performance Computer Architecture (HPCA), February 2007.
  Paper: pdf
  Talk: ppt, pdf
  

• Coherence Ordering for Ring-based Chip Multiprocessors,
  Michael R. Marty and Mark D. Hill,
  39th International Symposium on Microarchitecture (MICRO), December 2006.
  Paper: pdf
  Talk: ppt
  

• ASR: Adaptive Selective Replication for CMP Caches,
  Bradford M. Beckmann, Michael R. Marty, and David A. Wood,
  39th International Symposium on Microarchitecture (MICRO), December 2006.
  Paper: pdf
  Talk: ppt
  

• Improving Multiple-CMP Systems Using Token Coherence,
  Michael R. Marty, Jesse D. Bingham, Mark D. Hill, Alan J. Hu, Milo M.K. Martin and David A. Wood,
  International Symposium on High Performance Computer Architecture (HPCA), February 2005.
  Paper: pdf
  Talk: ppt
  Extended Talk: ppt

• Managing Wire Delay in Large Chip-Multiprocessor Caches,
  Bradford M. Beckmann and David A. Wood,
  37th International Symposium on Microarchitecture (MICRO), December 2004.
  Paper: pdf
  Talk: htm and ppt

• Using Speculation to Simplify Multiprocessor Design,
  Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, and David A. Wood,
  International Parallel and Distributed Processing Symposium (IPDPS), April 2004.
  Paper: pdf
  Talk: ppt

• Token Coherence: A New Framework for Shared-Memory Multiprocessors,
  Milo M.K. Martin, Mark D. Hill and David A. Wood,
  IEEE Micro Special Issue: Micro's Top Picks from Microarchitecture Conferences, November-December 2003.
  Paper: pdf
  Original ISCA03 Paper: pdf
  Token Coherence Bibliography: html
  

• Revisiting "Multiprocessors Should Support Simple Memory Consistency Models"
  (Talk to software memory consistency model researchers),
  Mark D. Hill,
  Dagstuhl Seminar 03431 on Hardware and Software Consistency Models: Programmability and Performance, October 2003.
  Abstract: txt
  Talk: ppt
  Original 1998 Paper: pdf

• Token Coherence: Decoupling Performance and Correctness,
  Milo M. K. Martin, Mark D. Hill, and David A. Wood,
  International Symposium on Computer Architecture (ISCA), June 2003.
  Paper: pdf
  Reference: ACM
  Talk: pdf, ppt
  Shorter IEEE Micro Top Picks Paper: pdf
  Token Coherence Bibliography: html
  

• Using Destination-Set Prediction to Improve the Latency/Bandwidth Tradeoff in Shared Memory Multiprocessors,
  Milo M. K. Martin, Pacia J. Harper, Daniel J. Sorin, Mark D. Hill, and David A. Wood,
  International Symposium on Computer Architecture (ISCA), June 2003.
  Paper: pdf
  Reference: ACM
  Talk: pdf, ppt

• Dynamic Verification of End-to-End Multiprocessor Invariants,
  Daniel J. Sorin, Mark D. Hill, and David A. Wood,
  International Conference on Dependable Systems and Networks (DSN, formerly FTCC), June 2003.
  Paper: pdf
  Talk: ppt

• Specifying and Verifying a Broadcast and a Multicast Snooping Cache Coherence Protocol,
  Daniel J. Sorin, Manoj Plakal, Anne E. Condon, Mark D. Hill, Milo M. K. Martin and David A. Wood,
  IEEE Transactions on Parallel and Distributed Systems, June 2002 (vol 13, number 6).
  (Previously available as Dept. of Computer Sciences Technical Report CS-TR-2000-1412, March 2000.)
  Paper: pdf
  Online protocol examples in html

• Bandwidth Adaptive Snooping,
  Milo M. K. Martin, Daniel J. Sorin, Mark D. Hill, and David A. Wood,
  8th International Symposium on High Performance Computer Architecture (HPCA), February 2002.
  Paper: pdf
  Talk: pdf and ppt

• Correctly Implementing Value Prediction in Microprocessors that Support Multithreading or Multiprocessing,
  Milo M. K. Martin, Daniel J. Sorin, Harold W. Cain, Mark D. Hill, and Mikko H. Lipasti,
  34th International Symposium on Microarchitecture (MICRO), December 2001.
  Paper: pdf
  Talk: pdf and ppt

• Timestamp Snooping: An Approach for Extending SMPs,
  Milo M. K. Martin, Daniel J. Sorin, Anastassia Ailamaki, Alaa R. Alameldeen, Ross M. Dickson, Carl J. Mauer, Kevin E. Moore, Manoj Plakal, Mark D. Hill, and David A. Wood,
  Ninth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), November 2000.
  Paper: pdf and ps
  Reference: ACM
  Talk: pdf

• A System-Level Specification Framework for I/O Architectures,
  Mark D. Hill, Anne E. Condon, Manoj Plakal, and Daniel J. Sorin,
  Symposium on Parallel Algorithms and Architectures (SPAA), June 1999.
  Paper: pdf and ps
  Talk: pdf and ps
  Extended Technical Report: pdf and ps
  Reference: ACM
  

• Using Lamport Clocks to Reason About Relaxed Memory Models,
  Anne E. Condon, Mark D. Hill, Manoj Plakal and Daniel J. Sorin,
  International Symposium on High-Performance Computer Architecture (HPCA), January 1999.
  Paper: pdf and ps
  Talk: pdf and ps

• Lamport Clocks: Verifying A Directory Cache-Coherence Protocol,
  Manoj Plakal, Daniel J. Sorin, Anne E. Condon and Mark D. Hill,
  Symposium on Parallel Algorithms and Architectures (SPAA), June 1998.
  Paper: pdf and ps
  Reference: ACM
  Talk: pdf and ps

• Multicast Snooping: A New Coherence Method Using a Multicast Address Network,
  E. Ender Bilir, Ross M. Dickson, Ying Hu, Manoj Plakal, Daniel J. Sorin, Mark D. Hill, and David A. Wood.
  International Symposium on Computer Architecture (ISCA), May 1999.
  Paper: pdf and ps
  Reference: ACM
  Talk: pdf and ps

• Multiprocessors Should Support Simple Memory Consistency Models,
  Mark D. Hill,
  IEEE Computer, August 1998.
  Paper: pdf
  2003 Dagstuhl Retrospective Talk: ppt

Deterministic Recording & Replay

• Two Hardware-based Approaches for Deterministic Multiprocessor Replay,
  Derek R. Hower, Pablo Montesinos, Luis Ceze, Mark D. Hill, and Josep Torrellas
  Communications of the ACM (CACM), June 2009.
  (Summarizes "Rerun" and "DeLorean" proposals from ISCA '08 for wider CACM audience.)
  Paper: pdf
  Technical Introduction by Jouppi: pdf
  

• Rerun: Exploiting Episodes for Lightweight Memory Race Recording,
  Derek R. Hower and Mark D. Hill
  International Symposium on Computer Architecture (ISCA), June 2008.
  Paper: pdf
  Talk: pptx ppt
  Recommended to CACM for wider audience: pdf
  

• A Hardware Memory Race Recorder for Deterministic Replay,
  Min Xu, Rastislav Bodik, and Mark D. Hill,
  IEEE Micro Special Issue: Micro's Top Picks from Microarchitecture Conferences, January-February 2007.
  (Summarizes ``Flight Data Recorder'' work from ISCA 2003 and ASPLOS 2006 papers).
  Paper: pdf
  Talk: ppt (based on Xu's 2006 Ph.D. Defense)
  

• A Regulated Transitive Reduction (RTR) for Longer Memory Race Recording,
  Min Xu, Rastislav Bodik and Mark D. Hill
  International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October 2006.
  Paper: pdf
  Reference: ACM (not yet available)
  Top Picks 2007 follow-on: pdf
  Talk: pdf, ppt

• A "Flight Data Recorder" for Enabling Full-system Multiprocessor Deterministic Replay,
  Min Xu, Rastislav Bodik and Mark D. Hill
  International Symposium on Computer Architecture (ISCA), June 2003.
  Paper: pdf
  Reference: ACM
  Top Picks 2007 follow-on: pdf
  Talk: pdf, ppt

Availability

• SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery,
  Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, and David A. Wood,
  International Symposium on Computer Architecture (ISCA), May 2002.
  Paper: pdf
  Reference: IEEE
  Talk: ppt

• Fast Checkpoint/Recovery to Support Kilo-Instruction Speculation and Hardware Fault Tolerance,
  Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, and David A. Wood,
  Dept. of Computer Sciences Technical Report CS-TR-2000-1420, October 2000.
  Technical Report: pdf and ps

Workload Analysis & Improvement

• A Serializability Violation Detector for Shared-Memory Server Programs,
  Min Xu, Rastislav Bodik and Mark D. Hill
  Programming Language Design and Implementation (PLDI), June 2005.
  Paper: pdf
  Reference: ACM
  Talk: pdf, ppt

• Memory System Behavior of Java-Based Middleware,
  Martin Karlsson, Kevin E. Moore, Erik Hagersten and David A. Wood,
  9th International Symposium on High Performance Computer Architecture (HPCA), February 2003.
  Paper: pdf
  Talk: pdf, ppt
  

• Evaluating a $2M Commercial Server on a $2K PC and Related Challenges (Invited Talk),
  Mark D. Hill,
  Workshop On Computer Architecture Evaluation using Commercial Workloads (CAECW), February 2004.
  Talk Abstract: pdf
  Talk: ppt

• Simulating a $2M Commercial Server on a $2K PC,
  Alaa R. Alameldeen, Milo M.K. Martin, Carl J. Mauer, Kevin E. Moore, Min Xu, Daniel J. Sorin, Mark D. Hill and David A. Wood,
  IEEE Computer, February 2003.
  Paper: pdf
  Talk: ppt

• Data Page Layouts for Relational Databases on Deep Memory Hierarchies,
  Anastassia Ailamaki, David J. DeWitt, and Mark D. Hill,
  The VLDB Journal, 11(3), 2002.
  Paper: pdf

• Memory Characterization of the ECperf Benchmark,
  Martin Karlsson, Kevin E. Moore, Erik Hagersten, and David A. Wood,
  Workload on Memory Performance Issues (WMPI), 2002.
  Paper: pdf.

• Evaluating Non-deterministic Multi-threaded Commercial Workloads,
  Alaa R. Alameldeen, Carl J. Mauer, Min Xu, Pacia J. Harper, Milo M.K. Martin, Daniel J. Sorin, Mark D. Hill and David A. Wood,
  Workshop On Computer Architecture Evaluation using Commercial Workloads (CAECW), February 2002.
  Paper: pdf
  Talk: pdf and ppt

• Weaving Relations for Cache Performance,
  Anastassia G. Ailamaki, David J. DeWitt, Mark D. Hill, and Marios Skounakis,
  International Conference on Very Large Databases (VLDB), 2001.
  Received VLDB 2001 Best Paper Award
  Paper: pdf
  Talk: ppt

• Cache Performance for Selected SPEC CPU2000 Benchmarks,
  Jason F. Cantin and Mark D. Hill,
  Computer Architecture News (CAN), September 2001.
  Reference: ACM
  

• Making Pointer-Based Data Structures Cache Conscious,
  Trishul M. Chilimbi, Mark D. Hill, and James R. Larus,
  IEEE Computer, December 2000.
  Paper: pdf.

• Concurrent Garbage Collection Using Program Slices on Multithreaded Processors,
  Manoj Plakal and Charles N. Fischer,
  The International Sympsosium on Memory Management (ISMM), October 2000 (co-located with OOPSLA 2000).
  Paper: pdf and ps

• Characterizing a Java Implementation of TPC-W,
  Todd Bezenek, Trey Cain, Ross Dickson, Timothy Heil, Milo Martin, Collin McCurdy, Ravi Rajwar, Eric Weglarz, Craig Zilles, and Mikko Lipasti,
  Workshop On Computer Architecture Evaluation Using Commercial Workloads (CAECW), January 2000.
  Talk: pdf
  Project Page: html

• DBMSs on a modern processor: Where does time go?,
  Anastassia Ailamaki, David J. DeWitt, Mark D. Hill, and David A. Wood,
  International Conference on Very Large Databases (VLDB), September 1999.
  Paper: pdf and ps
  Talk: ppt

• Cache-Conscious Structure Layout,
  Trishul M. Chilimbi, James R. Larus, and Mark D. Hill,
  Programming Language Design and Implementation (PLDI), 1999.
  Paper: pdf and ps. Reference: ACM
  

Modeling & Simulation

• Amdahl's Law in the Multicore Era,
  Mark D. Hill and Michael R. Marty
  Univ. of Wisconsin Computer Sciences Technical Report CS-TR-2007-1593, April 2007.
  Technical Report: pdf

• IPC Considered Harmful for Multiprocessor Workloads,
  Alaa R. Alameldeen and David A. Wood,
  IEEE Micro, Jul-Aug 2006.
  Paper: pdf
  

• GEMS: Multifacet's General Execution-driven Multiprocessor Simulator,
  Michael R. Marty, Bradford Beckmann, Luke Yen, Alaa R. Alameldeen, Min Xu, and Kevin Moore
  Tutorial at the International Symposium on Computer Architecture (ISCA), June 2005.
  Talk: ppt

• Multifacet's General Execution-driven Multiprocessor Simulator (GEMS) Toolset,
  Milo M.K. Martin, Daniel J. Sorin, Bradford M. Beckmann, Michael R. Marty, Min Xu, Alaa R. Alameldeen, Kevin E. Moore, Mark D. Hill, and David A. Wood,
  Computer Architecture News (CAN), September 2005.
  Paper: pdf
  Web Site: http://www.cs.wisc.edu/gems
  ISCA Tutorial Slides: ppt
  

• Interaction Cost: For when event counts just don't add up,
  Brian A. Fields, Rastislav Bodik, Mark D. Hill, and Chris J. Newburn,
  IEEE Micro Special Issue: Micro's Top Picks from Microarchitecture Conferences, November-December 2004.
  Paper: pdf
  Expanded TACO 2004 Journal Version: pdf
  

• Interaction Cost and Shotgun Profiling,
  Brian A. Fields, Rastislav Bodik, Mark D. Hill, and Chris J. Newburn,
  ACM Trans. on Architecture and Compiler Optimizations (TACO), September 2004.
  Paper: pdf
  Original Micro 2003 Conference Version: pdf
  Reference: ACM
  

• Addressing Workload Variability in Architectural Simulations,
  Alaa R. Alameldeen and David A. Wood,
  IEEE Micro Special Issue: Micro's Top Picks from Microarchitecture Conferences, November-December 2003.
  Paper: pdf
  Original HPCA03 Paper: pdf

• Using Interaction Costs for Microarchitectural Bottleneck Analysis,
  Brian A. Fields, Rastislav Bodik, Mark D. Hill, and Chris J. Newburn,
  36th International Symposium on Microarchitecture (MICRO), December 2003.
  Paper: pdf
  Talk: ppt
  Expanded TACO 2004 Journal Version: pdf
  

• Challenges in Computer Architecture Evaluation,
  Kevin Skadron, Margaret Martonosi, David I. August, Mark D. Hill, David J. Lilja, and Vijay S. Pai.
  IEEE Computer, August 2003.
  Paper: pdf

• Analytic Evaluation of Shared-Memory Architectures,
  Daniel J. Sorin, Jonathan L. Lemon, Derek L. Eager, and Mary K. Vernon,
  Transactions on Parallel and Distributed Systems, February 2003.
  Submitted version available as University of Wisconsin Dept. of Computer Sciences Technical Report CS-TR-2000-1404b, January 2000.
  Paper: pdf
  Technical Report: pdf

• Variability in Architectural Simulations of Multi-threaded Workloads,
  Alaa R. Alameldeen and David A. Wood,
  9th International Symposium on High Performance Computer Architecture (HPCA), February 2003.
  Paper: pdf
  Talk: ppt, pdf

• Full-System Timing-First Simulation,
  Carl J. Mauer, Mark D. Hill, and David A. Wood,
  ACM SIGMETRICS, June 2002.
  Paper: pdf
  Reference: ACM
  Talk: pdf and ppt

• Facile: A Language and Compiler For High-Performance Processor Simulators,
  Eric C. Schnarr, James R. Larus, and Mark D. Hill,
  Programming Language Design and Implementation (PLDI), 2001.
  Paper: pdf
  Reference: ACM
  

• AMVA Techniques for High Service Time Variability,
  Derek L. Eager, Daniel J. Sorin, and Mary K. Vernon,
  ACM SIGMETRICS, June 2000.
  Paper: pdf and ps

• Fast and Portable Parallel Architecture Simulators: Wisconsin Wind Tunnel II,
  Shubhendu S. Mukherjee, Steven K. Reinhardt, Babak Falsafi, Mike Litzkow, Steven Huss-Lederman, Mark D. Hill, James R. Larus, and David A. Wood,
  IEEE Concurrency, October-December 2000.
  Paper: pdf.

Miscellaneous

• Single-Threaded vs. Multithreaded: Where Should We Focus?,
  Joel Emer, Mark D. Hill, Yale N. Patt, Joshua J, Yi, Derek Chiou, and Resit Sedag,
  IEEE Micro Special Issue: Computer Archtecture Debates, November-December 2007.
  Paper: pdf.

• Future Computer Advances are Between a Rock (Slow Memory) and a Hard Place (Multithreading)
  (Talk to CSTB and US government agencies),
  Mark D. Hill,
  The National Academies's Computer Science and Telecommunications Board (CSTB) Meeting, October 2004.
  Talk: ppt

• A Future for Parallel Computer Architectures
  (Keynote talk to parallel software researchers),
  Mark D. Hill,
  International Conference on Parallel Processing (ICPP), August 2004.
  Talk: ppt

• Adaptive Cache Compression for High-Performance Processors,
  Alaa R. Alameldeen and David A. Wood,
  International Symposium on Computer Architecture (ISCA), June 2004.
  Paper: pdf
  Talk: ppt
  Details of the compression algorithm are available in:
  
  • Frequent Pattern Compression: A Significance-Based Compression Scheme for L2 Caches,
    Alaa R. Alameldeen and David A. Wood,
    Dept. of Computer Sciences Technical Report CS-TR-2004-1500, April 2004.
    Technical Report: pdf

• TLC: Transmission Line Caches,
  Bradford M. Beckmann and David A. Wood,
  36th International Symposium on Microarchitecture (MICRO), December 2003.
  Paper: pdf
  Talk: htm and ppt

• Slack: Maximizing Performance Under Technological Constraints,
  Brian Fields, Rastislav Bodik, and Mark D. Hill,
  International Symposium on Computer Architecture (ISCA), 2002.
  Paper: pdf
  Reference: IEEE
  Talk: ppt

• Harnessing Moore's Law
  (Talk to computer science undergraduates),
  Mark D. Hill,
  Several venues, 2002-03.
  Abstract: txt
  Talk: ppt

• Estimating the Selectivity of XML Path Expressions for Internet Scale Applications,
  Ashraf Aboulnaga, Alaa R. Alameldeen, and Jeffrey F. Naughton,
  International Conference on Very Large Databases (VLDB), 2001.
  Paper: pdf.

• How Computer Architecture Trends May Affect Future Distributed Systems: From InfiniBand Clusters to Inter-Processor Speculation
  (Keynote talk for researchers in theoretical aspects distributed systems),
  Mark D. Hill,
  Symposium on Principles of Distributed Computing (PODC), July 2000.
  Abstract: pdf
  Talk: ppt

• Readings in Computer Architecture,
  Mark D. Hill, Norman P. Jouppi, and Gurindar S. Sohi, Morgan Kaufmann Publishers, ISBN 1-55860-539-8, 2000. Near-final versions of:
  Preface: pdf and ps
  Table of Contents: pdf and ps
  Web Component: html or html mirror