Wisconsin Publications

• Most Multifacet Publications use GEMS

• GEMS Summary Paper:

Multifacet's General Execution-driven Multiprocessor Simulator (GEMS) Toolset,
Milo M.K. Martin, Daniel J. Sorin, Bradford M. Beckmann, Michael R. Marty, Min Xu, Alaa R. Alameldeen, Kevin E. Moore, Mark D. Hill, and David A. Wood,
Computer Architecture News (CAN), September 2005.
Paper: pdf
Web Site: http://www.cs.wisc.edu/gems
ISCA Tutorial Slides: ppt

External Publications

Split Hardware Transactions: True nesting of transactions using best-effort hardware transactional memory Yossi Lev and Jan-Willem Maessen (Best Paper from PPoPP 2008).

Runtime Validation of Memory Ordering Using Constraint Graph Checking Kaiyu Chen, Sharad Malik, Priyadarsan Patra, High Performance Computer Architecture (HPCA 2008), February 2008.

Hybrid Transactional Memory to Accelerate Safe Lock-Based Transactions Enrique Vallejo, Tim Harris, Adrian Cristal, Osman Unsal, Mateo Valero, 3rd ACM SIGPLAN Workshop on Transactional Computing (TRANSACT 2008), February 2008.

The Adaptive Transactional Memory Test Platform: A Tool for Experimenting with Transactional Code for Rock Mark Moir, Kevin Moore, Dan Nussbaum, 3rd ACM SIGPLAN Workshop on Transactional Computing (TRANSACT 2008), February 2008.

Applications of the Adaptive Transactional Memory Test Platform Dave Dice, Maurice Herlihy, Doug Lea, Yossi Lev, Victor Luchangco, Wayne Mesard, Mark Moir, Kevin Moore, Dan Nussbaum, 3rd ACM SIGPLAN Workshop on Transactional Computing (TRANSACT 2008), February 2008.

Effective Management of DRAM Bandwidth in Multicore Processors Nauman Rafique, Won-Taek Lim, Mithuna Thottethodi, The Sixteenth International Conference on Parallel Architectures and Compilation Techniques (PACT) Brasov, Romania, September 15-19, 2007

I2SEMS: Interconnects-Independent Security Enhanced Shared Memory Multiprocessor Systems ,Manhee Lee, Minseon Ahn and Eun Jung Kim, The Sixteenth International Conference on Parallel Architectures and Compilation Techniques (PACT) Brasov, Romania, September 15-19, 2007

Rotary Router: An Efficient Architecture for CMP Interconnection Networks, Pablo Abad, Valentin Puente, Pablo Prieto, and Jose Angel Gregorio, Proceedings of the 34th International Symposium on Computer Architecture (ISCA), June 2007.

An Integrated Hardware-Software Approach to Flexible Transactional Memory, Arrvindh Shriraman, Michael F. Spear, Hemayet Hossain, Virendra J. Marathe, Sandhya Dwarkadas, and Michael L. Scott, Proceedings of the 34th International Symposium on Computer Architecture (ISCA), June 2007.

Making the Fast Case Common and the Uncommon Case Simple in Unbounded Transactional Memory, Colin Blundell, Joe Devietti, E Christopher Lewis, and Milo M. K. Martin, Proceedings of the 34th International Symposium on Computer Architecture (ISCA), June 2007.

ParallAX: An Architecture for Real-Time Physics, Tom Yeh, Petros Faloutsos, Sanjay Patel, and Glenn Reinman, Proceedings of the 34th International Symposium on Computer Architecture (ISCA), June 2007.

An Effective Starvation Avoidance Mechanism to Enhance the Token Coherence Protocol, Blas Cuesta, Antonio Robles, and Jose Duato, Proceedings of the 15th EUROMICRO International Conference on Parallel, Distributed and Network-Based Processing (PDP'07), 2007.

PhTM: Phased Transactional Memory, Yosef Lev, Mark Moir, and Dan Nussbaum, The Second ACM SIGPLAN Workshop on Transactional Computing (TRANSACT-07)

NZTM: Nonblocking Zero-Indirection Transactional Memory, Fuad Tabba, Cong Wang, and James R. Goodman, The Second ACM SIGPLAN Workshop on Transactional Computing (TRANSACT-07)

Error Detection Via Online Checking of Cache Coherence with Token Coherence Signatures , Albert Meixner and Daniel J. Sorin, Proceedings of the 13th International Symposium on High Performance Computer Architecture (HPCA), February 2007.

A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures, R. Fernndez-Pascual, J. Garca, M. Acacio, and J. Duato, Proceedings of the 13th International Symposium on High Performance Computer Architecture (HPCA), February 2007.

Hybrid Transactional Memory, Peter Damron, Alexandra Fedorova, Yossi Lev, Victor Luchangco, Mark Moir, and Dan Nussbaum, Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October 2006.

Perceptron Based Consumer Prediction in Shared-Memory Multiprocessors, Sean Leventhal and Manoj Franklin, Proceedings of the 24th International Conference on Computer Design (ICCD), October 2006.

Architectural Support for Operating System-Driven CMP Cache Management, Nauman Rafique, Won-Taek Lim, and Mithuna Thottethodi, Proceedings of the 15th Parallel Architectures and Compilation Techniques (PACT), September 2006.

Spin Detection Hardware for Improved Management of Multithreaded Systems. , Tong Li, Alvin R. Lebeck, and Daniel J. Sorin, IEEE Transactions on Parallel and Distributed Systems (TPDS), volume 17, number 6, June 2006.

Cooperative Caching for Chip Multiprocessors, Jichuan Chang and Gurindar S. Sohi, International Symposium on Computer Architecture (ISCA), June 2006.

Dynamic Verification of Memory Consistency in Cache-Coherence Multithreaded Computer Architectures." , Albert Meixner and Daniel J. Sorin, International Conference on Dependable Systems and Networks (DSN), June 2006.

Interconnect-Aware Coherence Protocols for Chip Multiprocessors, Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, and John B. Carter, International Symposium on Computer Architecture (ISCA), June 2006.

Dynamic Verification of Sequential Consistency. , Albert Meixner and Daniel J. Sorin, International Symposium on Computer Architecture (ISCA), June 2005.