Programming accelerators is challenging. Not only do programmers reason about parallelism, but unlike traditional CPU programming, they also must reason about data movement and transformation. Multicore and multiprocessor CPUs hide this movement and transformation through two mechanisms: virtual addressing and cache coherence. In this talk, I focus on one current high-performance accelerator--integrated general-purpose GPUs--as an example. I show that directly using CPU techniques on high performance accelerators, like the GPU, is impractical. GPUs can sustain many more memory requests per cycle which causes significant performance degradation for both address translation (up to 10x slowdown) and cache coherence (up to 4x slowdown). I present two techniques to bring these vital CPU capabilities to high-performance accelerators.
First, I show that providing virtual address translation for integrated GPUs is feasible by leveraging the GPU architecture to filter most TLB accesses and using a high-bandwidth page table walker. Second, I will show that providing fine-grained coherence for integrated GPUs is practical by exploiting the spatial locality of GPU workloads and using a coarse-grained coherence mechanism. With these two techniques, virtual addressing and cache coherence can be feasibly implemented on high performance accelerators which will ease programmer adoption of these emerging platforms.
Jason Lowe-Power is a Ph.D. candidate at the University of Wisconsin-Madison in the Computer Sciences department advised by Mark Hill and David Wood. He received a B.Sc. in Computer Science from Georgia Institute of Technology in 2010 and a M.Sc. in Computer Science from UW-Madison in 2013. His research focuses on increasing the energy efficiency and of computing systems with a focus on exposing energy-efficient accelerators to all programmers. His research also targets reducing the energy needed for analytic database operations used by companies like Amazon, Netflix, Google, Target, etc. to analyze and deeply understand their customers’ needs. He has completed internships at Advanced Micro Devices Research and Georgia Tech Research Institute. He was awarded the Wisconsin Distinguished Graduate Fellowship Cisco Computer Sciences Award in 2014 and 2015. Jason is scheduled to graduate in May 2017.