Modularizing the Microprocessor Core to Outperform Traditional Out-of-Order

Tuesday, September 13, 2016 -
4:00pm to 5:00pm
TBD (tentatively CS 1240)

Speaker Name: 

Karu Sankaralingam

Speaker Institution: 

UW-Madison

Cookies: 

No

Description: 

Abstract: General purpose cores are becoming increasingly difficult to improve because of device scaling limitations and architecture complexity. The "generic" OOO design principles provide little remove for significant performance improvements or power reduction and is unappealingly monolithic.  In this talk, I'll describe a new paradigm for designing high-performance processors that are power constrained by revisiting the fundamental principles of processor design. Our called ExoCore uses three simple insights: i) programs execute in distinct phases with well defined program behaviors; ii) we can build highly efficient execution engines that excel at different behavior in both performance and power compared to a generic OOO core; iii) these engines can be integrated in a modular fashion to existing simple processor cores.

We have designed, and in simulation, studied various programs and behaviors and defined a first-generation ExoCore processor which achieves performance and energy efficiency well beyond existing state-of-art microprocessors. On a wide range of general workloads (SpecINT, PARSEC, Mediabench etc.), an in-order core-based ExoCore nearly matches the performance of a quad-issue OOO core, and a dual issue OOO core based-ExoCore can exceed the performance of a 6-wide OOO core, both at half the power.  ExoCore designs provide a path forward for single-thread performance and energy efficiency with low design cost. I will conclude with our ambitious plan to build a small prototype ExoCore chip and discussions with application experts to identify more behaviors.

Bio: Karu Sankaralingam is an associate professor in the computer sciences department at the University of Wisconsin-Madison. His research interests include architecture, open source hardware, and software issues for massively parallel computation systems. His group has built the MIAOW open source GPGPU, and the DySER extension to OpenSPARC. He is a recipient of the IEEE TCCA Young Computer Architecture Award in 2012, an NSF CAREER award in 2009, the Emil H Steiger Distinguished Teaching award in 2014, and the Letters and Science Philip R. Certain - Gary Sandefur Distinguished Faculty Award in 2013. He has authored multiple IEEE Micro Top Picks papers, best paper awards, multiple CACM Research Highlights papers and nominations, and has 15 patents/applications. He earned a PhD from The University of Texas at Austin in December 2006.