Exploring the Potential of Heterogeneous Von Neumann/Dataflow Execution Models

Tuesday, June 9, 2015 -
4:45pm to 5:30pm

Speaker Name: 

Tony Nowatzki

Speaker Institution: 

UW Madison




General purpose processors (GPPs), from small inorder
designs to many-issue out-of-order, incur large power over-
heads which must be addressed for future technology gener-
ations. Major sources of overhead include structures which
dynamically extract the data-dependence graph or maintain
precise state. Considering irregular workloads, current spe-
cialization approaches either heavily curtail performance, or
provide simply too little benefit. Interestingly, well known
explicit-dataflow architectures eliminate these overheads by
directly executing the data-dependence graph and eschew-
ing instruction-precise recoverability. However, even after
decades of research, dataflow architectures have yet to come
into prominence as a solution. We attribute this to a lack
of effective control speculation and the latency overhead of
explicit communication, which is crippling for certain codes.
This paper makes the observation that if both out-of-order
and explicit-dataflow were available in one processor, many
types of GPP cores can benefit from dynamically switching
during certain phases of an application’s lifetime. Analysis
reveals that an ideal explicit-dataflow engine could be prof-
itable for more than half of instructions, providing significant
performance and energy improvements. The challenge is to
achieve these benefits without introducing excess hardware
complexity. To this end, we propose the Specialization Engine
for Explicit-Dataflow (SEED). Integrated with an inorder core,
we see 1.67× performance and 1.65× energy benefits, with
an Out-Of-Order (OOO) dual-issue core we see 1.33× and
1.70×, and with a quad-issue OOO, 1.14× and 1.54×.