Computer Architecture Seminar: The Energy Challenges of Caching and Moving Data On Your Chip

Tuesday, April 28, 2015 -
12:00pm to 1:00pm
CS 1240

Speaker Name: 

Arrvindh Shriraman

Speaker Institution: 

Simon Fraser University

Cookies: 

Yes

Cookies Location: 

CS 1240

Description: 

Today, power constraints determine our ability to keep compute units active and busy. Interestingly, storing and moving the data used and produced by the computation consumes more energy than the computation itself. Whether multicores, GPUs or fixed-function accelerators, how we move and feed the computation units has critical impact on the programming model and the compute efficiency. We observe that unlike the latency overhead of the data movement which could potentially be hidden, energy overhead dictates that we need to fundamentally reduce waste in the memory hierarchy.

Our research focuses on cache designs and coherence protocols that improve the energy efficiency of the memory hierarchy by adapting the data storage and movement to the application characteristics. I will particularly focus on the design of a new coherence substrate, Temporal Coherence, that helps build energy efficient cache hierarchies for fixed-function accelerators and GPUs. I will demonstrate how temporal coherence can help offload fine-grain program regions to fixed-function hardware accelerators and help move data efficiently between the accelerators. The overall lessons from our work will highlight the importance of optimizing the memory hierarchy with a focus on energy efficiency.

Bio: Arrvindh is an Assistant Professor in the School of Computing Sciences at Simon Fraser University where he has been a faculty member since 2011. His current research focuses on the energy efficient caches and coherence protocols for fixed-function accelerators and GPUs. His recent paper on GPU coherence has been selected as "Top Picks" by IEEE Micro Magazine. He received an IBM Faculty Award in 2014 for his work in cache coherence for accelerators. ​