Data Centric Computing in Emerging Technologies: A PCM-CMOS In-Memory Computing Engine

Wednesday, February 4, 2015 -
4:00pm to 5:00pm
CS 1240

Speaker Name: 

Jing Li

Speaker Institution: 

UW Madison





The confluence of disruptive technologies beyond CMOS and "Big Data" workloads calls for a fundamental paradigm shift from homogenous compute-centric system to heterogeneous data-centric system for better innovation, competition and productivity. With the objective of rethinking data-centric system design from ground up, I will first present a PCM-CMOS in-memory computing engine which is inspired by the concept of ternary content addressable memory (TCAM) and enabled by emerging memory technology i.e., phase change memory (PCM). In particular, a fully-functional heterogeneous chip was designed and fabricated for the first time, achieving >10x cell area reduction compared to homogenous CMOS-based design at the same technology node. It fundamentally blurs the boundary between computation and storage. It can be configured as a compute unit ─ a high performance search engine (or any logic function to perform direct data-flow computation). It can also be configured as a storage media i.e., high throughput storage class memory. In addition, it exploits tremendous bandwidth available on chip and puts compute close to data sources to reduce communication cost. Thus, it is an attractive solution for many data-intensive applications e.g., genome matching, intrusion detection, etc.. However, design with heterogeneous technologies poses new challenges due to the severely degraded signal margin introduced by technology itself. To address these challenges, I will present two enabling techniques: 1) a clocked self-referenced sensing scheme and 2) a two-bit encoding, which can also improve algorithmic mapping for better hardware utilization. With these techniques, the fabricated chip can reliably operate at very low voltage (750mV). The work was recognized as a highlighted paper by Symp. on VLSI Circuits 2013 and an invited paper for JSSC'14. In the second part, I will briefly highlight two techniques to move further into a more cost-effective design based on variable-bit storage.


Dr. Jing Li is an assistant professor at the department of
Electrical and Computer Engineering, University of Wisconsin
Madison. She spent her early career at IBM T. J. Watson Research
Center as a Research Staff Member after obtaining her PhD degree
from Purdue University in 2009. Her general research interest is
developing new computing paradigm, driven either by /technologies/
(from bottom-up) or by /workload/s (from top-down) or by both. Her
primary area of interests is "/*everything about memory*" with a
strong emphasis on “design for transformation” rather than “design
for replacement”, /including but are not limited to new computing
concepts/models (e.g., near-/in-memory computing,
associative/congnitive computing, reconfigurable computing, etc.),
hardware prototyping, memory/storage subsystem, memory architecture
and interface protocol, circuit design and CAD methodology, memory
technology (device/integration/material), etc. that can transform
today's hardware-software hierarchy. The key differentiator of her
research is that besides modelings and simulations, she puts
additional emphasis on /*real hardware demostration*/ through
architecting, designing and testing new hardware prototypes.
Previously, she demostrated the world's first heterogeneous chip
that fundamentally blurs the boundary between computation and
storage. The work was recognized as a highlighted paper by Symp. on
/VLSI Circuits 2013/ and an invited paper for /JSSC'14/.

She has received IBM Research Division Outstanding Technical
Achievement Award in 2012 for successfully achieving CEO milestone,
multiple invention achievement awards and high value patent
application awards from IBM from 2010-2014, IBM Ph.D. Fellowship
Award in 2008, Meissner Fellowship in 2004 from Purdue University,
etc. She has published more than 35 technical papers in referred
journals and conferences and has more than 35 patents filed/issued.
Besides academic impacts, her contributions to IBM’s IP portfolio
have been essential to multiple lucrative partnerships. She won the
Best Paper Award from IEEE Circuits and Systems Society VLSI
Transactions for her contribution in STT RAM. She has been
reviewers for numerous journals and conferences, and has been
serving on the technical committee for Design Automation Conference
(DAC) since 2011. As organizing committee, she is the technical
chair at 2015 International Memory Workshop (IMW) - a premier
industry memory conference with world-wide memory vendors