Today’s multicore chips commonly implement shared memory with cache
coherence as low-level support for operating systems and application
software. Technology trends continue to enable the scaling of the number
of (processor) cores per chip. Because conventional wisdom says that the
coherence does not scale well to many cores, some prognosticators
predict the end of coherence.

This talk refutes this conventional wisdom by showing one way to scale
on-chip cache coherence with bounded costs by combining known techniques
such as: shared caches augmented to track cached copies, explicit cache
eviction notifications, and hierarchical design. Based upon our
scalability analysis of this proof-of-concept design, we predict that
on-chip coherence and the programming convenience and compatibility it
provides are here to stay.

See paper by Milo M. K. Martin, Mark D. Hill, & Daniel J. Sorin, Comm.
of the ACM, July 2012, http://dx.doi.org/10.1145/2209249.2209269