Given that modern and future compute devices will integrate a growing number of components on a single chip, the importance of high-performance and low-power on-chip communication is on the rise. However, given the diversity and complexity of components on these highly-integrated chips, investigating chip-level architecture designs aimed at achieving these performance and power objectives is very difficult. Current and future systems will see increasing and diversifying communication demands as the systems and common applications change to meet the demands of consumers.

In this talk, I will discuss the current state-of-the-art in on-chip communication performance and power evaluation methodologies, including my prior work, Netrace, which is a trace-based, dependency-driven approach to evaluating interconnect fabrics of new and emerging chips. In addition to motivating these techniques by pointing out their benefits, I will describe their disadvantages, and opportunities to improve future evaluation techniques.

For more information about Netrace: http://www.cs.utexas.edu/~netrace/

Joel Hestness is a PhD student transferring to UW from the University of Texas at Austin, where he started is PhD working with Prof. Steve Keckler. Joel's research focuses on on-chip communication and networks, and more recently on heterogeneous computing chips. For more information, check out his site: http://www.cs.utexas.edu/~hestness/