This is a practice talk for ISCA.

Our analysis shows that many “big-memory” server workloads,
such as databases, in-memory caches, and graph analytics, pay a
high cost for page-based virtual memory. They consume as much
as 10% of execution cycles on TLB misses, even using large pages.
On the other hand, we find that these workloads use read-write
permission on most pages, are provisioned not to swap, and rarely
benefit from the full flexibility of page-based virtual memory.
To remove the TLB miss overhead for big-memory workloads,
we propose mapping part of a process’s linear virtual address space
with a direct segment, while page mapping the rest of the virtual
address space. Direct segments use minimal hardware—base, limit
and offset registers per core—to map contiguous virtual memory
regions directly to contiguous physical memory. They eliminate
the possibility of TLB misses for key data structures such as
database buffer pools and in-memory key-value stores. Memory
mapped by a direct segment may be converted back to paging
when needed. We prototype direct-segment software support for x86-64
in Linux and emulate direct-segment hardware. For our workloads,
direct segments eliminate almost all TLB misses and reduce the
execution time wasted on TLB misses to less than 0.5%.