Speaker: Karu Sankaralingam

Abstract:

The era of faster, smaller, greener (more power efficient) transistors
in every successive generation appears to be dead. Instead, processor
architects and microarchitects are going to be partially burdened with
power-efficiently and energy-efficiently improving performance with
technology scaling providing density improvements "alone".

In this talk, I will describe the DySER project which investigates
ways for dynamically specializing datapaths to energy-efficiently
improve performance. DySER attempts to provide a truly general purpose
accelerator, avoiding radical changes to software development, ISA, or
microarchitecture. Our key insights are the following. First,
applications execute in phases and these phases can be determined by
creating a path-tree of basic-blocks rooted at the inner-most
loop. Second, specialized datapaths corresponding to these path-trees,
can be constructed by interconnecting a set of heterogeneous
computation units with a circuit-switched network. On simulation-based
results for the SPEC and Parsec benchmarks, the DySER architecture
provides geometric mean speedup of 2.1X (1.15X to 10X), and geometric
mean energy reduction of 40% (up to 70%). On highly tuned
throughput kernels, DySER outperforms hand-optimized SSE code.
To demonstrate the architecture is practical, we have completed
a prototype FPGA implementation of DySER integrated with the
OpenSPARC processor. This design runs unmodified Linux
and runs actual applications generated by the DySER compiler.

The talk will provide the main insights behind the DySER architecture,
quantitative results, and outline challenges and possibilities in
using it in a modern
microprocessor and particularly as an accelerator in a mobile processor.