Abstract: Since 2005, processor designers have increased core counts to exploit Moore’s Law scaling, rather than focusing on single-core performance. The failure of Dennard scaling, to which the shift to multicore parts is partially a response, may soon limit multicore scaling just as single-core scaling has been curtailed. This talk will cover models used to examine multicore scaling limits by combining device scaling, single-core scaling, and multicore scaling to measure the speedup potential for a set of parallel workloads for the next five technology generations.  The multicore designs we study include single threaded CPU-like and massively threaded GPU-like multicore chip organizations with symmetric, asymmetric, dynamic, and composed topologies. The study shows that regardless of chip organization and topology, multicore scaling is power limited to a degree not widely appreciated by the computing community. 

 

Bio: I am a Computer Science PhD student at University of Wisconsin-Madison working with Professor Karu Sankaralingam.  My research interests include future-looking computer architectures, the application of analytic modeling to performance and power projections, and the impacts of transistor scaling and new technologies.