CALL FOR PAPERS 

Active'17: Second International Workshop on Active Middleware on Modern Hardware 
(In Conjunction with ACM/IFIP/USENIX Middleware 2017). 
Las Vegas, Nevada, Dec 11-15, 2017

https://active-conf.github.io/


OBJECTIVES:
Building upon the success of the First International Active Workshop
at ICDE conference, the second edition of Active will focus primarily on Active
Middleware. The objective of this one-day workshop is to investigate opportunities
in exploiting the crossroad between novel hardware technologies and middleware:
active (compute-intensive) technologies such as active memory, active networking, 
and active storage for accelerating distributed data-intensive workloads, and 
investigate issues in enabling these capabilities by revisiting the entire 
middleware stack hosted on cloud. Our mission is to inspire a creative workshop 
atmosphere, where everyone contributes to a lively discussion during the entire 
course of the event.


SCOPE:
Recent popularity of Big Data applications has renewed interest in developing
and optimizing distributed data-intensive workloads. In addition to the traditional
scientific computing domain, Big Data phenomena are observed in a variety
of new domains such as Internet of Things (IoT), social analytic, personalized
health and precision medicine, bioinformatics, energy informatics, and
emergency response and disaster management.  The Big Data workloads
are characterized by unprecedented volumes and velocity of data, both historic
and transient, very high-speed data flows (e.g., from sensor networks), and
diverse variety of data from completely unstructured text documents, to
structured relational tables or matrices, to photos and videos. Analyzing vast
quantities of such complex data (partially powered by machine learning) is
becoming as important as the traditional massive-scale data management.

Unfortunately, existing approaches to solve data-intensive problems are
woefully inadequate to address the challenges raised by the Big Data
applications. Specifically, these approaches require data to be processed to
be moved near the computing resources while studying the role of middleware
paradigm to this end. These data movement costs can be prohibitive for large
data sets such as those observed in the aforementioned workloads. One way to
address this problem is to bring virtualized computing resources closer to data,
whether it is at rest or in motion. This is the premise of "active" middleware
that enable key data storage and communication components to compute on
the persistent or transient data.

Although prototypes of systems with active technologies are currently
available, there is a very limited exploitation of their capabilities
in real-life problems.  The proposed workshop aims to evaluate different
aspects of the active middleware stack and understand impact of active
technologies on different applications workloads. Specifically, the
workshop hopes to understand the role of modern hardware to enable
active medium (whether network, storage, memory) over the entire path
and the lifecycle of data especially as today's distributed systems opt to
hierarchies of storage and memory. Furthermore, we aim to revisit the
interplay between algorithmic modeling, compiler and programming languages,
virtualized runtime systems and environments, and hardware implementations,
for effective exploitation of active technologies.



TOPICS COVERED INCLUDE, BUT ARE NOT LIMITED TO:
1) Novel Architectures and Architectural Extensions
-Type of "active" components by exploiting emerging modern hardware such as FPGAs, GPUs, and ASICs
-Active blockchains fabric (shared, replicated and distributed ledgers)
-Active and (weak) consistent distributed caching (hierarchical volatile and non-volatile memory) by exploiting merging -hardware such as HTM, RDMA, NVM
-Active distributed replication and high-availability

2)Transaction on Modern Hardware
-Distributed transaction models and the role of ACID
-Transactional memory
-Transactional caching using RDMA
-Transactions in rack- and geo-scale architectures
-Transactions in rack- and geo-scale architectures

3) Distributed Coordination and Consistency Models
-Hardware-assisted agreement protocols (2PC, 3PC, Quorum, Consensus, PAXOS)
-Fast hardware-aware commit protocols (e.g., RDMA)
-Instant hardware-aware recovery, fail-over, replication protocols (e.g., RDMA)
-Hardware-assisted ordering (e.g., group commit protocols)
-Hardware-assisted reliable and persistent network
-Hardware-assisted network and sites fault-tolerance and high-availability

4) Middleware on software-hardware-system co-design
-Co-processor design by offloading computation to accelerators
-Co-placement design by placing accelerator on the path of data (partial computation or best effort computation)
-Co-design virtualization on cloud
-Co-design privacy and security concerns
-Co-design approximate in-network computing

5) Distributed programming paradigms and algoritmic modeling
-Exposing active elements to the programmers---language extensions/directives/pragmas, libraries, and intrinsic
-Accelerator-based programming abstractions (offloading, placement, cooperation)
-Code generations and domain-specific languages (DSLs)
-Novel abstract execution cost models over heterogeneous hardware
-Novel compiler optimization on heterogeneous platforms
-Persistent programming paradigm
-Persistent abstractions for networks
-Middleware abstraction for cross-platform interoperability
-Middleware abstraction to unity heterogeneous hardware

6) Middleware Adaptability
-Adaptive and evolutionary approaches
-Workload-adaptability (scalability and elasticity)
-Hardware-assisted data partitioning, clustering, replication, and distribution
-Energy-adaptability and energy-aware middleware architectures


Submission Dates: 
Paper Submission Deadline: August 31, 2017 
Notification of Acceptance: September 28, 2017
Camera Ready: October 16, 2017
											

WORKSHOP CO-CHAIRS:
Mohammad Sadoghi (Purdue University)
Ilia Petrov (Reutlingen University)

PUBLICITY CHAIR: 
Kaiwen Zhang (Technical University of Munich)

PROGRAM COMMITTEE:
Carsten Binnig (Brown University)
Sebastian Breß (German Research Center for Artificial Intelligence)
Bingsheng He (National University of Singapore)
Alessandro Margara (Politecnico di Milano)
Tilmann Rabl (TU Berlin)
Kai-Uwe Sattler (Ilmenau University of Technology)
Jens Teubner (TU Dortmund)
Vassilis J. Tsotras (University of California - Riverside)
Stratis Viglas (Google Inc., University of Edinburgh)


							
STRUCTURE:
Active 2017 will be organized along three tracks (all accepted papers 
will be presented at the workshop):

1) Regular Research Papers: These papers should report original research 
results or significant case studies/experimental surveys. They should be at most 8 pages.

2) Position Papers: These papers should report novel research directions 
or identify challenging problems. They should be at most 4 pages.

3) Abstracts: These papers should report on preliminary and ongoing work 
or exploratory research directions. They should be at most 1 page.

All submissions must be prepared according to the Middleware formatting guidelines.

						
PROCEEDINGS:
All accepted papers will appear in a Middleware 2017 companion proceedings,
which will be available in the ACM Digital Library.


SUBMISSION INFORMATION: 
Papers have to be submitted electronically as PDF files via HotCRP: 
https://active17.hotcrp.com/