%Z -------------------------------------------------------------------------
%Z
%Z	Refer/bib bibliographic entries for the 17th
%Z	INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE
%Z	(1990) created by Julie Fingerson and Mark D. Hill
%Z 
%Z	These entries are correct to the best of our knowledge,
%Z	but we accept no responsibility for the consequences of
%Z	any errors.  Email corrections to hoffman@cs.wisc.edu.
%Z	Last change:  Tue Mar 28 15:51:01 CST 1995
%Z
%Z -------------------------------------------------------------------------
%Z

%T Weak Ordering-A New Definition
%A Sarita V. Adve
%A Mark D. Hill
%J Proc. 17th Annual Symposium on Computer Architecture
%D May 1990
%P 2-14

%T Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors 
%A Kourosh Gharachorloo
%A Daniel Lenoski
%A James Laudon
%A Phillip Gibbons
%A Anoop Gupta
%A John Hennessy
%J Proc. 17th Annual Symposium on Computer Architecture
%D May 1990
%P 15-26

%T Synchronization with Multiprocessor Caches
%A Joonwon Lee
%A Umakishore Ramachandran
%J Proc. 17th Annual Symposium on Computer Architecture
%D May 1990
%P 27-37

%T Dynamic Processor Allocation in Hypercube Computers
%A Po-Jen Chuang
%A Nian-Feng Tzeng
%J Proc. 17th Annual Symposium on Computer Architecture
%D May 1990
%P 40-49   

%T A New Approach to Fast Control of r2 x r2 3-Stage Benes Networks of r x r Crossbar Switches
%A Abdou Youssef
%A Bruch Arden
%J Proc. 17th Annual Symposium on Computer Architecture
%D May 1990
%P 50-59 

%T Virtual-Channel Flow Control
%A William J. Dally 
%J Proc. 17th Annual Symposium on Computer Architecture
%D May 1990
%P 60-68

%T Supporting Systolic and Memory Communciation in iWarp
%A Shekhar Borkar
%A Robert Cohn
%A George Cox
%A Thomas Gross
%A H. T. Kung
%A Monica Lam
%A Margie Levine
%A Brian Moore
%A Wire Moore
%A Craig Peterson
%A Jim Susman
%A Jim Sutton 
%A John Urbanski
%A Jon Webb
%J Proc. 17th Annual Symposium on Computer Architecture
%D May 1990
%P 70-81

%T Monsoon: An Explicit Token-Store Architecture
%A Gregory M. Papadopoulos
%A David E. Culler
%J Proc. 17th Annual Symposium on Computer Architecture
%D May 1990
%P 82-91

%T The K2 Parallel Processor: Architecture and Hardware Implementation
%A Marco Annaratone
%A Marco Fillo
%A Kiyoshi Nakabayashi
%A Marc Viredaz
%J Proc. 17th Annual Symposium on Computer Architecture
%D May 1990
%P 92-101

%T APRIL: A Processor Architecture for Multiprocessing
%A Anant Agarwal
%A Beng-Hong Lim
%A David Kranz
%A John Kubiatowicz
%J Proc. 17th Annual Symposium on Computer Architecture
%D May 1990
%P 104-114

%T PLUS: A Distributed Shared-Memory System
%A Roberto Bisiani
%A Mosur Ravishankar
%J Proc. 17th Annual Symposium on Computer Architecture
%D May 1990
%P 115-124

%T Adaptive Software Cache Management for Distributed Shared Memory Architectures
%A John K. Bennett
%A John B. Carter
%A Willy Zwaenepoel
%J Proc. 17th Annual Symposium on Computer Architecture
%D May 1990
%P 125-134

%T An Empirical Evaluation of Two Memory-Efficient Directory Methods 
%A Brian W. O'Krafka
%A A. Richard Newton
%J Proc. 17th Annual Symposium on Computer Architecture
%D May 1990
%P 138-147

%T The Directory-Based Cache Coherence Protocol for the DASH Multiprocessor
%A Daniel Lenoski
%A James Laudon
%A Kourosh Gharachorloo
%A Anoop Gupta
%A John Hennessy
%J Proc. 17th Annual Symposium on Computer Architecture
%D May 1990
%P 148-159

%T The Performance Impact of Block Sizes and Fetch Strategies
%A Steven Przybylski
%J Proc. 17th Annual Symposium on Computer Architecture
%D May 1990
%P 160-169

%T Performance Comparison of Load/Store and Symmetric Instruction Set Architectures
%A D. Alpert
%A A. Averbuch
%A O. Danieli
%J Proc. 17th Annual Symposium on Computer Architecture
%D May 1990
%P 172-181

%T Reducing the Cost of Branches by Using Registers
%A Jack W. Davidson
%A David B. Whalley 
%J Proc. 17th Annual Symposium on Computer Architecture
%D May 1990
%P 182-191

%T An Investigation of Static Versus Dynamic Scheduling
%A Carl E. Love
%A Harry F. Jordan
%J Proc. 17th Annual Symposium on Computer Architecture
%D May 1990
%P 192-201

%T VAX Vector Architecture
%A Dileep Bhandarkar
%A Richard Brunner
%J Proc. 17th Annual Symposium on Computer Architecture
%D May 1990
%P 204-215 

%T Multiple Instruction Issue in the NonStop Cyclone Processor
%A Robert W. Horst
%A Richard L. Harris
%A Robert L. Jardine
%J Proc. 17th Annual Symposium on Computer Architecture
%D May 1990
%P 216-226

%T Performance of an OLTP Application on Symmetry Multiprocessor System
%A Shreekant S. Thakkar
%A Mark Sweiger
%J Proc. 17th Annual Symposium on Computer Architecture
%D May 1990
%P 228-238

%T The Impact of Synchronization and Granularity on Parallel Systems
%A Ding-Kai Chen
%A Hong-Men Su
%A Pen-Chung Yew
%J Proc. 17th Annual Symposium on Computer Architecture
%D May 1990
%P 239-248

%T Trace-Driven Simulations for a Two-Level Cache Design in Open Bus Systems
%A Hakon O. Bugge
%A Ernst H. Kristiansen
%A Bjorn O. Bakka
%J Proc. 17th Annual Symposium on Computer Architecture
%D May 1990
%P 250-259

%T Performance Measurement and Trace Driven Simulation of Parallel CAD and Numeric Applications on a Hypercube Multicomputer
%A Jiun-Ming Hsu
%A Prithviraj Banerjee
%J Proc. 17th Annual Symposium on Computer Architecture
%D May 1990
%P 260-269

%T Generation and Analysis of Very Long Address Traces
%A Anita Borg
%A R. E. Kessler
%A David W. Wall
%J Proc. 17th Annual Symposium on Computer Architecture
%D May 1990
%P 270-279

%T Fast Prolog with an Extended General Purpose Architecture
%A Bruce K. Holmer
%A Barton Sano
%A Michael Carlton
%A Peter Van Roy
%A Ralph Haygood
%A William R. Bush
%A Alvin M. Despain
%A Joan M. Pendleton
%A Tep Dobry
%J Proc. 17th Annual Symposium on Computer Architecture
%D May 1990
%P 282-291

%T Architectural Support for the Management of Tightly-Coupled Fine-Grain Goals in Flat Concurrent Prolog
%A Leon Alkalaj
%A Tomas Lang
%A Milos Ercegovac
%J Proc. 17th Annual Symposium on Computer Architecture
%D May 1990
%P 292-301

%T Balance in Architectural Design
%A Samuel Ho
%A Lawrence Snyder
%J Proc. 17th Annual Symposium on Computer Architecture
%D May 1990
%P 302-310

%T A Study of I/O Behavior of Perfect Benchmarks on a Multiprocessor
%A A. L. Narasimha Reddy
%A Prithviraj Banerjee
%J Proc. 17th Annual Symposium on Computer Architecture
%D May 1990
%P 312-321

%T Maximizing Performance in a Striped Disk Array
%A Peter M. Chen
%A David A. Patterson
%J Proc. 17th Annual Symposium on Computer Architecture
%D May 1990
%P 322-331

%T A Distributed I/O Architecture for HARTS
%A Kang G. Shin
%A Greg Dykema
%J Proc. 17th Annual Symposium on Computer Architecture
%D May 1990
%P 332-342

%T Boosting Beyond Static Scheduling in a Superscalar Processor
%A Michael D. Smith
%A Monica S. Lam
%A Mark A. Horowitz
%J Proc. 17th Annual Symposium on Computer Architecture
%D May 1990
%P 344-354

%T The TLB Slice--A Low-Cost High-Speed Address Translation Mechanism
%A George Taylor
%A Peter Davies
%A Michael Farmwald
%J Proc. 17th Annual Symposium on Computer Architecture
%D May 1990
%P 355-363

%T Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers
%A Norman P. Jouppi
%J Proc. 17th Annual Symposium on Computer Architecture
%D May 1990
%P 364-373