%Z -------------------------------------------------------------------------
%Z
%Z	Refer/bib bibliographic entries for the 16th
%Z	INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE
%Z	(1989) created by Julie Fingerson and Mark D. Hill
%Z 
%Z	These entries are correct to the best of our knowledge,
%Z	but we accept no responsibility for the consequences of
%Z	any errors.  Email corrections to hoffman@cs.wisc.edu.
%Z	Last change:  Tue Mar 28 15:51:01 CST 1995
%Z
%Z -------------------------------------------------------------------------
%Z

%T Evaluating the Performance of Four Snooping Cache Coherency Protocols
%A Susan J. Eggers
%A Randy H. Katz
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989
%P 2-15 

%T Multi-level Shared Caching Techniques for Scalability in VMP-MC
%A David R. Cheriton
%A Hendrik A. Goosen
%A Patrick D. Boyle
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 16-24

%T Design and Performance of a Coherent Cache for Parallel Logic Programming Architectures
%A Atsuhiro Goto
%A Akira Matsumoto
%A Evan Tick
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 25-33

%T The Epsilon Dataflow Processor
%A V. G. Grafe
%A G. S. Davidson
%A J. E. Hoch
%A V. P. Holmes
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 36-45

%T An Architecture of a Dataflow Single Chip Processor
%A Shuichi Sakai
%A Yoshinori Yamaguchi
%A Kei Hiraki
%A Yuetsu Kodama
%A Toshitsugu Yuba
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 46-53

%T Exploiting Data Parallelism in Signal Processing on a Data Flow Machine
%A Peter Nitezki
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 54-61

%T Architectural Mechanisms To Sparse Vector Processing
%A R. N. Ibbett
%A T. M. Hopkins
%A K. I. M. McKinnon
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 64-71

%T A Dynamic Storage Scheme for Conflict-Free Vector Access
%A D. T. Harper III
%A D. A. Linebarger
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 72-77

%T SIMP (Single Instruction stream/Multiple Instruction Pipelining): A Novel High-Speed Single-Processor Architecture
%A Kazuaki Murakami
%A Naohiko Irie
%A Morihiro Kuga
%A Shinji Tomita
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 78-85

%T 2-D SIMD Algorithms in the Perfect Shuffle Networks
%A Yosi Ben-Asher
%A David Egozi
%A Assaf Schuster
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 88-95

%T Systematic Hardware Adaptation of Systolic Algorithms
%A Miguel Valero-Garcia
%A Juan J. Navarro
%A Jose M. Llaberia
%A Mateo Valero
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 96-104

%T Task Migration in Hypercube Multiprocessors
%A Ming-Syan Chen
%A Kang G. Shin
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 105-111

%T Characteristics of Performance-Optimal Multi-Level Cache Hierarchies
%A Steven Przybylski
%A Mark Horowitz
%A John Hennessy
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 114-121

%T Supporting Reference and Dirty Bits in SPUR's Virtual Address Cache
%A David A. Wood
%A Randy H. Katz
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 122-130

%T Inexpensive Implementations of Set-Associativity
%A R. E. Kessler
%A Richard Jooss
%A Alvin Lebeck
%A Mark D. Hill
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 131-139

%T Organization and Performance of a Two-Level Virtual-Real Cache Hierarchy
%A Wen-Hann Wang
%A Jean-Loup Baer
%A Henry M. Levy
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 140-148

%T High Performance Communications in Processor Networks
%A Jesshope CR
%A Miller PR
%A Yantchev JT
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 150-157

%T Introducing Memory into Switch Elements of Multiprocessor Interconnection Networks
%A Haim E. Mizrahi
%A Jean-Loup Baer
%A Edward D. Lazowska
%A John Zahorjan
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 158-166

%T Using Feedback to Control Tree Saturation in Multistage Interconnection Networks
%A Steven L. Scott
%A Gurindar S. Sohi
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 167-176

%T Constructing Replicated Systems Using Processors with Point-to-Point Communication Links
%A Paul D. Ezhilchelvan
%A Santosh K. Shrivastava
%A Alan Tully
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 177-184

%T KCM: A Knowledge Crunching Machine
%A H. Benker
%A J. M. Beacco
%A S. Bescos
%A M. Dorochevsky
%A Th. Jeffre
%A A. Pohlmann
%A J. Noye
%A B. Poterie
%A A. Sexton
%A J. C. Syre
%A O. Thibault
%A G. Watzlawik
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 186-194

%T A High Performance Prolog Processor with Multiple Function Units
%A Ashok Singhal
%A Yale N. Patt
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 195-202

%T Evaluation of Memory System for Integrated Prolog Processor IPP
%A M. Morioka
%A S. Yamaguchi
%A T. Bandoh
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 203-210 

%T A Type Driven Hardware Engine for Prolog Clause Retrieval over a Large Knowledge Base
%A Kam-Fai Wong
%A M. Howard Williams
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 211-222

%T Comparing Software and Hardware Schemes For Reducing the Cost of Branches
%A Wen-mei W. Hwu
%A Thomas M. Conte
%A Pohua P. Chang
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 224-233

%T Improving Performance of Small On-Chip Instruction Caches
%A Matthew K. Farrens
%A Andrew R. Pleszkun
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 234-241

%T Achieving High Instruction Cache Performance with an Optimizing Compiler
%A Wen-mei W. Hwu
%A Pohua P. Chang
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 242-251

%T The Impact of Code Density on Instruction Cache Performance
%A Peter Steenkiste
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 252-259

%T Can Dataflow Subsume von Neumann Computing?
%A Rishiyur S. Nikhil
%A Arvind
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 262-272

%T Exploring the Benefits of Multiple Hardware Contexts in a Multiprocessor Architecture: Preliminary Results
%A Wolf-Dietrich Weber 
%A Anoop Gupta
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 273-280

%T Architectural and Organizational Tradeoffs in the Design of the MultiTitan CPU
%A Norman P. Jouppi
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 281-289

%T Run-Time Checking in Lisp by Integrating Memory Addressing and Range Checking
%A Mitsuhisa Sato
%A Shuichi Ichikawa
%A Eiichi Goto
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 290-297

%T Multiple vs. Wide Shared Bus Multiprocessors
%A Andy Hopper
%A Alan Jones
%A Dimitris Lioupis
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 300-306

%T Performance Measurements on a Commercial Multiprocessor Running Parallel Code
%A Marco Annaratone
%A Roland Ruhl
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 307-314

%T Interprocessor Communication Speed and Performance in Distributed-memory Parallel Processors
%A Marco Annaratone
%A Calude Pommerell
%A Roland Ruhl
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 315-324

%T Analysis of Computation-Communication Issues in Dynamic Dataflow Architectures
%A Dipak Ghosal
%A Satish K. Tripathi
%A Laxmi N. Bhuyan
%A Hong Jiang
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 325-333

%T Logic Simulation on Massively Parallel Architectures
%A Saul A. Kravitz
%A Randal E. Bryant
%A Rob A. Rutenbar
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 336-343

%T R256: A Research Parallel Processor for Scientific Computation
%A Tomoo Fukazawa
%A Takashi Kimura
%A Masaaki Tomizawa
%A Kazumitsu Takeda
%A Yoshitaka Itoh
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 344-351

%T A Three-Port/Three-Access Register File for Concurrent Processing and I/O Communication in a RISC-Like Graphics Engine
%A M. L. Anido
%A D. J. Allerton
%A E. J. Zaluska
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 354-361

%T An Architecture Framework for Application-Specific and Scalable Architectures
%A J. M. Mulder
%A R. J. Portier
%A A. Srivastava
%A R. in 't Velt
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 362-369

%T Perfect Latin Squares and Parallel Array Access
%A Kichul Kim
%A V. K. Prasanna Kumar
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 372-379

%T An Aperiodic Storage Scheme to Reduce Memory Conflicts in Vector Processors
%A Shlomo Weiss
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 380-386

%T Analysis of Vector Access Performance on Skewed Interleaved Memory
%A Chuen-Liang Chen
%A Chung-Kai Liao
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 387-394

%T Adaptive Backoff Synchronization Techniques
%A Anant Agarwal
%A Mathews Cherian
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 396-406

%T A Cache Consistency Protocol for Multiprocessors with Multistage Networks
%A Per Stenstrom
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 407-415

%T On Data Synchronizations for Multiprocessors
%A Hong-Men Su
%A Pen-Chung Yew 
%J Proc. 16th Annual Symposium on Computer Architecture
%D May 1989 
%P 416-423