%Z -------------------------------------------------------------------------
%Z
%Z	Refer/bib bibliographic entries for the 13th
%Z	INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE
%Z	(1986) created by Julie Fingerson and Mark D. Hill
%Z 
%Z	These entries are correct to the best of our knowledge,
%Z	but we accept no responsibility for the consequences of
%Z	any errors.  Email corrections to hoffman@cs.wisc.edu.
%Z	Last change:  Tue Mar 28 15:51:01 CST 1995
%Z
%Z -------------------------------------------------------------------------
%Z

%T A Model and an Architecture for a Relational Knowledge Base
%A Haruo Yokota
%A Hidenori Itoh
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 2-9

%T Implementation and Evaluation of a List-Processing-Oriented Data Flow Machine
%A Makoto Amamiya
%A Masaru Takesue
%A Ryuzo Hasegawa
%A Hirohide Mikami
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 10-19

%T A New String Search Hardware Architecture for VLSI
%A K. Takahashi
%A H. Yamada
%A H. Nagai
%A K. Matsumi
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 20-27

%T Parallel Algorithms and Architectures for Rule-Based Systems
%A Anoop Gupta
%A Charles Forgy
%A Allen Newell
%A Robert Wedig
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 28-37

%T Concert: Design of a Multiprocessor Development System  
%A Robert H. Halstead Jr.
%A Thomas L. Anderson
%A Randy B. Osborne
%A Thomas L. Sterling
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 40-48 

%T Memory Requirements for Balanced Computer Architectures   
%A H. T. Kung
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 49-54

%T Graph Allocation in Static Dataflow Systems
%A Yang-Chang Hong
%A Thomas H. Payne
%A Le Baron O. Ferguson
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 55-64

%T Software Implementation of a Recursive Fault Tolerance Algorithm on a Network of Computers
%A Prathima Agrawal
%A Rakesh Agrawal
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 65-72

%T Microprogrammable Processor for Object-Oriented Architecture
%A Tohru Nojiri
%A Shumpei Kawasaki
%A Kousuke Sakoda
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 74-81

%T An Instruction Fetch Unit for a Graph Reduction Machine
%A Shreekant S. Thakkar
%A William E. Hostmann
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 82-91

%T Fast Object-Oriented Procedure Calls: Lessons from the Intel 432
%A Edward F. Gehringer
%A Robert P. Colwell
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 92-101

%T On Coupling Many Small Systems for Transaction Processing
%A Daniel M. Dias
%A Balakrishna R. Iyer
%A Philip S. Yu
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 104-110

%T Performance Measurement of Paging Behavior in Multiprogramming Systems
%A Mohammad I. Malkawi
%A Janak H. Patel
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 111-118

%T ATUM: A New Technique for Capturing Address Traces Using Microcode
%A Anant Agarwal
%A Richard L. Sites
%A Mark Horowitz
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 119-127

%T Experimenting With EPILOG: Some Results and Preliminary Conclusions
%A Michael J. Wise
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 130-139

%T A Unification Processor Based on a Uniformly Structured Cellular Hardware
%A Yasuro Shobatake
%A Hideo Aiso
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 140-148

%T The Architecture and Preliminary Evaluation Results of the Experimental Parallel Inference Machine PIM-D
%A Noriyoshi Ito
%A Masatoshi Sato
%A Eiji Kuno
%A Kazuaki Rokusawa
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 149-156

%T An Efficient Routing Control Unit for the SIGMA Network E(4)
%A Andre Seznec 
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 158-168

%T REYSM, A High Performance, Low Power Multi-Microprocessor Bus
%A J. D. Nicoud
%A K. Skala
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 169-174

%T The Extra Stage Gamma Network
%A Kyungsook Yoon Lee
%A Wael Hegazy
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 175-182

%T Evaluation of the FACOM ALPHA Lisp Machine
%A Masanobu Yuhara
%A Aikira Hattori
%A Masashi Niwa
%A Mitsuhiro Kishimoto
%A Hiromu Hayashi
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 184-190

%T An Architecture for Efficient Lisp List Access
%A A. R. Pleszkun
%A M. J. Thazhuthaveetil
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 191-198

%T Evaluation of the SPUR Lisp Architecture
%A George S. Taylor
%A Paul N. Hilfinger
%A James R. Larus
%A David A. Patterson
%A Benjamin G. Zorn
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 199 paper found on page 444-452

%T A Functional Level Simulation Engine of MAN-YO: A Special Purpose Parallel Machine for Logic Design Automation 
%A Toshiyuki Nakata
%A Nobuhiko Koike
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 202-208

%T Exploiting Parallelism in a Switch-Level Simulation Machine
%A Edward H. Frank
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 209-215

%T A Hardware Accelerator for Speech Recognition Algorithms
%A T.S. Anantharaman
%A R. Bisiani
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 216-223

%T Evaluation of a Prototype Data Flow Processor of the SIGMA-1 for Scientific Computations
%A Toshio Shimada
%A Kei Hiraki
%A Kenji Nishida
%A Satoshi Sekiguchi
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 226-234

%T Stored Data Structures on the Manchester Dataflow Machine
%A J. Sargeant
%A C.C. Kirkham
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 235-242

%T A Salable Dataflow Structure Store
%A K. Kawakami
%A J.R. Gurd
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 243-250

%T AT2=O(N log4 N), T=O(log N) Fast Fourier Transform in a Light Connected 3-Dimensional VLSI
%A Makoto Hasegawa
%A Yoshiharu Shigei
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 252-260

%T Modular Architecture for High Performance Implementation of FFT Algorithm
%A K. Sapiecha
%A R. Jarocki
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 261-270

%T Computing Size-Independent Matrix Problems on Systolic Array Processors
%A Juan J. Navarro
%A Jose M. Llaberia
%A Mateo Valero
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 271-278

%T A Computer with Low-Level Parallelism QA-2: Its Applications to 3-D Graphics and Prolog/Lisp Machines
%A Shinji Tomita
%A Kiyoshi Shibayama
%A Toshiyuki Nakata
%A Shinji Yuasa
%A Hiroshi Hagiwara
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 280-289

%T VLSI Oriented Asynchronous Architecture
%A Masaharu Hirayama
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 290-296

%T HPSm, a High Performance Restricted Data Flow Architecture Having Minimal Functionality
%A Wen-mei Hwu
%A Yale N. Patt
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 297-306

%T On Design of Rotary Array Communication and Wavefront-Driven Algorithms for Solving Large-Scale Band-Limited Matrix Equations
%A Kenji Onaga
%A Takahiro Takechi
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 308-315

%T A Computer Architecture for Dynamic Finite Element Analysis
%A Leonard M. Napolitano Jr.
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 316-323

%T Performance Evaluation of Vector Accesses in Parallel Memories Using a Skewed Storage Scheme
%A D. T. Harper III
%A J. R. Jump
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 324-328

%T Pseudo MIMD Array Processor - AAP2
%A Toshio Kondo
%A Toshio Tsuchiya
%A Yoshihiro Kitamura
%A Yoshi Sugiyama
%A Takashi Kimura
%A Takayoshi Nakashima
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 330-337

%T Scan Line Array Processors for Image Computation
%A Allan L. Fisher
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 338-345

%T Warp Architecture and Implementation
%A Marco Annaratone
%A Emmanuel Arnould
%A Thomas Gross
%A H.T. Kung
%A Monica S. Lam
%A Onat Menzilcioglu
%A Ken Sarocky
%A Jon A. Webb 
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 346-356

%T An In-Cache Address Translation Mechanism
%A David A. Wood
%A Susan J. Eggers
%A Garth Gibson
%A Mark D. Hill
%A Joan M. Pendleton
%A Scott A. Ritchie
%A George S. Taylor
%A Randy H. Katz
%A David A. Patterson
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 358-365

%T Software-Controlled Caches in the VMP Multiprocessor
%A David R. Cheriton
%A Gert A. Slavenburg
%A Patrick D. Boyle
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 366-374

%T On the Use of Registers vs. Cache to Minimize Memory Traffic
%A James R. Goodman
%A Wei-Chung Hsu
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 375-383

%T Highly Concurrent Scalar Processing
%A Peter Y. T. Hsu
%A Edward S. Davidson
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 386-395

%T Reducing the Cost of Branches
%A Scott McFarling
%A John Hennessy
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 396-403

%T Optimal Pipelining in Supercomputers
%A Steven R. Kunkel
%A James E. Smith
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 404-411

%T A Class of Compatible Cache Consistency Protocols and their Support by the IEEE Futurebus
%A Paul Sweazey
%A Alan Jay Smith
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 414-423

%T Multiprocessor Cache Synchronization: Issues, Innovations, Evolution
%A Philip Bitar
%A Alvin M. Despain
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 424-433

%T Memory Access Buffering in Multiprocessors
%A Michel Dubois
%A Christoph Scheurich
%A Faye Briggs
%J Proc. 13th Annual Symposium on Computer Architecture
%D June 1986
%P 434-442