%Z -------------------------------------------------------------------------
%Z
%Z	Refer/bib bibliographic entries for the 12th
%Z	INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE
%Z	(1985) created by Julie Fingerson and Mark D. Hill
%Z 
%Z	These entries are correct to the best of our knowledge,
%Z	but we accept no responsibility for the consequences of
%Z	any errors.  Email corrections to hoffman@cs.wisc.edu.
%Z	Last change:  Thu Mar 30 14:32:06 CST 1995
%Z
%Z -------------------------------------------------------------------------
%Z

%T Array Processor with Multiple Broadcasting
%A V. K. Prasanna Kumar
%A C. S. Raghavendra
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 2-10

%T Matrix Multiplication in an Interleaved Array Processing Architecture
%A G. Wolf
%A J. R. Jump
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 11-17

%T PIPE: A VLSI Decoupled Architecture
%A James R. Goodman
%A Jian-tu Hsieh
%A Koujuch Liou
%A Andrew R. Pleszkun
%A P. B. Schechter
%A Honesty C. Young
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 20-27

%T TIDBITS: Speedup Via Time-Delay Bit-Slicing in ALU Design for VLSI Technology
%A Peter Y. T. Hsu
%A Joseph T. Rahmeh
%A Edward S. Davidson 
%A Jacob A. Abraham
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 28-35

%T Implementation of Precise Interrupts in Pipelined Processors
%A James E. Smith
%A Andrew R. Pleszkun
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 36-44

%T High-Speed Top-of-Stack Scheme for VLSI Processor: a Management Algorithm and Its Analysis
%A Makoto Hasegawa
%A Yoshiharu Shigei
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 48-54

%T Analyzing Multiple Register Sets
%A Charles Y. Hitchcock III
%A H. M. Brinkley Sprunt
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 55-63

%T Cache Evaluation and the Impact of Workload Choice
%A Alan Jay Smith
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 64-73

%T Architecture of the Symbolics 3600
%A David A. Moon
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 76-83

%T Parallel Garbage Collection Without Synchronization Overhead
%A Ashwin Ram
%A Janak H. Patel
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 84-90

%T An Efficient LISP-Execution Architecture with a New Representation for List Structures
%A Gurindar S. Sohi
%A Edward S. Davidson
%A Janak H. Patel
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 91-98

%T (SM)2-II: A New Version of the Sparse Matrix Solving Machine
%A Hideharu Amano
%A Taisuke Boku
%A Tomohiro Kudoh
%A Hideo Aiso
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 100-107

%T The GF11 Supercomputer
%A John Beetem
%A Monty Denneau
%A Don Weingarten
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 108-115

%T Models for Use in the Design of Macro-Pipelined Parallel Processors
%A Bradley Warren Smith
%A Howard Jay Siegel 
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 116-123

%T Issues Related to MIMD Shared-memory Computers: The NYU Ultracomputer Approach
%A Jan Edler
%A Allan Gottlieb
%A Clyde P. Kruskal
%A Kevin P. McAuliffe
%A Larry Rudolph
%A Marc Snir
%A Patricia J. Teller
%A James Wilson
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 126-135

%T MU6V: A Parallel Vector Processing System
%A R. N. Ibbett
%A P. C. Capon
%A N. P. Topham
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 136-144

%T A Decentralized Control, Highly Concurrent Multiprocessor
%A Stephen F. Lundstrom
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 145-151

%T An Object Oriented Architecture
%A William J. Dally
%A James T. Kajiya
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 154-161

%T Tagged Architecture: How Compelling Are its Advantages?
%A Edward F. Gehringer
%A J. Leslie Keedy
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 162-170

%T VM/4: ACOS-4 Virtual Machine Architecture
%A S. Nanba
%A N. Ohno
%A H. Kubo
%A H. Morisue
%A T. Ohshima
%A H. Yamagishi
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 171-178

%T Performance Studies of a Prolog Machine Architecture
%A T. P. Dobry
%A A. M. Despain
%A Y. N. Patt
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 180-190

%T Design of a High-speed Prolog Machine (HPM)
%A Ryosei Nakazaki
%A Akihiko Konagaya
%A Shin'ichi Habata
%A Hideo Shimazu
%A Mamoru Umemura
%A Masahiro Yamamoto
%A Minoru Yokota
%A Takashi Chikayama
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 191-197

%T A Hardware Unification Unit: Design and Analysis
%A Nam Sung Woo
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 198-205

%T Performance of a Message-Based Multiprocessor
%A John Sanguinetti
%A B. Kumar
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 208 (See pages 424-425)

%T The FLEX/32 Multicomputer
%A Nicholas Matelan
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 209-213

%T Closely Coupled Asynchronous Hierarchical and Parallel Processing in an Open Architecture
%A Dick Naedel
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 215-220

%T Parallel Processing as a Language Design Problem
%A Jim Savage
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 221-224

%T Improvements in Multiprocessor System Design
%A David P. Rodgers
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 225-231

%T The Sequoia Computer: A Fault-Tolerant Tightly-Coupled Multiprocessor Architecture
%A Peter B. Mark
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 232

%T The Synapse N+1 System: Architectural Characteristics and Performance Data of a Tightly-Coupled Multiprocessor System
%A Elliot Nestle
%A Armond Inselberg
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 233-239

%T An Architecture for High Volume Transaction Processing
%A Robert W. Horst
%A Timothy C. K. Chou
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 240-245

%T A Hardware Pipeline Algorithm for Relational Database Operation and Its Implementation Using Dedicated Hardware
%A Shigeo Kamiya
%A Kazuhide Iwata
%A Hiroshi Sakai
%A Susumu Matsuda
%A Shigeki Shibayama
%A Kunio Murakami
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 250-257

%T A Distributed Multiple-Response Resolver for Value-Ordered Retrieval
%A Dik Lun Lee
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 258-265

%T Dynamic, Distributed Resource Configuration on SW-Banyans
%A John Feo
%A Roy Jenevein
%A J. C. Browne
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 268-275

%T Implementing A Cache Consistency Protocol
%A R. H. Katz
%A S. J. Eggers
%A D. A. Wood
%A C. L. Perkins
%A R. G. Sheldon
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 276-283

%T A Technique for Reducing Synchronization Overhead in Large Scale Multiprocessors
%A Zhiyuan Li
%A Walid Abu-Sufah
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 284-291

%T The transputer
%A Colin Whitby Strevens
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 292-300

%T A Systolic Multiplier Unit and Its VLSI Design
%A A. R. Hurson
%A B. Shirazi
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 302-309

%T A Language for the Simulation of Systolic Architectures
%A Rami Melhem
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 310-314

%T A Versatile Systolic Array for Matrix Computations
%A Henry Y. H. Chuang
%A Guo He
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 315-322

%T The Hughes Data Flow Multiprocessor: Architecture for Efficient Signal and Data Processing
%A Rex Vedder
%A Dennis Finn
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 324-332

%T An Abstract Parallel Graph Reduction Machine
%A Kenneth R. Traub
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 333-341

%T Data Flow on a Queue Machine
%A Bruno R. Preiss
%A V. C. Hamacher
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 342-351

%T Methods for Handling Structures in Data-Flow Systems
%A J. L. Gaudiot
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 352-358

%T The de Bruijn Multiprocessor Network: A Versatile Sorting Network
%A M. R. Samatham
%A D. K. Pradhan
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 360-367

%T A Fault-Tolerant Scheme for Multistage Interconnection Networks
%A Nian-Feng Tzeng
%A Pen-Chung Yew
%A Chuan-Qi Zhu
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 368-375 

%T Design and Analysis of Fault-Tolerant Multistage Interconnection Networks With Low Link Complexity
%A V. P. Kumar
%A S. M. Reddy
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 376-386

%T The Performance Analysis of Partitioned Circuit Switched Multistage Interconnection Networks
%A Nathaniel J. Davis IV
%A Howard Jay Siegel
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 387-394

%T The Influence of Parallel Decomposition Strategies on the Performance of Multiprocessor Systems
%A Dalibor Vrsalovic
%A Edward F. Gehringer
%A Zary Z. Segall
%A Daniel P. Siewiorek
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 396-405

%T Performance Prediction Tools for Cedar: A Multiprocessor Supercomputer
%A Walid Abu-Sufah
%A Alex Y. Kwok
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 406-413

%T Analysis and Simulation of Multiplexed Single-Bus Networks With and Without Buffering
%A Jose M. Llaberia
%A Mateo Valero 
%A Enrique Herrada
%A Jesus Labarta
%J Proc. 12th Annual Symposium on Computer Architecture
%D June 1985
%P 414-421