%Z -------------------------------------------------------------------------
%Z
%Z	Refer/bib bibliographic entries for the 11th
%Z	INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE
%Z	(1984) created by Julie Fingerson and Mark D. Hill
%Z 
%Z	These entries are correct to the best of our knowledge,
%Z	but we accept no responsibility for the consequences of
%Z	any errors.  Email corrections to hoffman@cs.wisc.edu.
%Z	Last change:  Thu Mar 30 14:32:06 CST 1995
%Z
%Z -------------------------------------------------------------------------
%Z

%T A Vector and Array Multiprocessor Extension of the Sylvan Architecture
%A F. J. Burkowski
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 4-11

%T The Pringle Parallel Computer
%A Alejandro Kapauan
%A J. Timothy Field
%A Dennis B. Gannon
%A Lawrence Snyder
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 12-20

%T A State-of-the-Art SIMD Two-Dimensional FFT Array Processor
%A Mehrad Yasrebi
%A G. J. Lipovski 
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 21-27

%T The Architecture of REPLICA-A Special-Purpose Computer System for Active Multi-Sensory Perception of 3-Dimensional Objects
%A Y.-W. Ma
%A R. Krishnamurti
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 30-37

%T A Generalized Object Display Processor Architecture
%A Samuel M. Goldwasser
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 38-47

%T A Special Purpose LSI Processor Using the DDA Algorithm for Image Transformation
%A Katsura Kawakami
%A Shigeo Shimazaki
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 48-54

%T The Status of MANIP-A Multicomputer Architecture for Solving Combinatorial Extremum-Search Problems
%A Benjamin W. Wah
%A Guo-Jie Li
%A Chee-Fen Yu
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 56-63

%T The Schuss Filter: A Processor for Non-Numerical Data Processing
%A R. Gonzalez-Rubio
%A J. Rohmer
%A D. Terral
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 64-73

%T The Design and Implementation of a VLSI Chess Move Generator
%A Carl Ebeling
%A Andrew Palay
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 74-80

%T Performance Analysis of Circuit Switching Baseline Interconnection Networks
%A Manjai Lee
%A Chuan-lin Wu
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 82-90

%T The Importance of Being Square
%A Clyde P. Kruskal
%A Marc Snir
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 91-98

%T Connection Principles for Multipath Packet Switching Networks
%A Chi-Yuan Chin
%A Kai Hwang
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 99-108 

%T Instruction Issue Logic for Pipelined Supercomputers
%A Shlomo Weiss
%A James E. Smith
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 110-118

%T The Reduction of Branch Instruction Execution Overhead Using Structured Control Flow
%A Robert G. Wedig
%A Marc A. Rose
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 119-125

%T Fast Execution of Loops With IF Statements
%A Utpal Banerjee
%A Daniel D. Gajski
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 126-132

%T A Parallel Pipelined Relational Query Processor: An Architectural Overview
%A Daniel Gajski
%A Won Kim
%A Shinya Fushimi
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 134-141

%T An Efficient VLSI Dictionary Machine
%A Arun K. Somani
%A Vinod K. Agarwal
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 142-150

%T Dictionary Machines With a Small Number of Processors
%A Allan L. Fisher
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 151-156

%T Experimental Evaluation of On-Chip Microprocessor Cache Memories
%A Mark D. Hill
%A Alan Jay Smith
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 158-166

%T The Use of Static Column RAM as a Memory Hierarchy
%A James R. Goodman
%A Men-chow Chiang
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 167-174

%T The Design of an Object Oriented Architecture
%A Yutaka Ishikawa
%A Mario Tokoro
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 178-187

%T Architecture of SOAR: Smalltalk on a RISC
%A David Ungar
%A Ricki Blau
%A Peter Foley
%A Dain Samples
%A David Patterson
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 188-197

%T Design of Instruction Set Architectures for Support of High-Level Languages 
%A Pradip Bose
%A Edward S. Davidson
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 198-206

%T Automatic Synthesis of Systolic Arrays from Uniform Recurrent Equations
%A Patrice Quinton
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 208-214

%T Multi-Dimensional Systolic Networks for Discrete Fourier Transform
%A Chang nian Zhang
%A David Y.Y. Yun
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 215-222

%T Data Broadcasting in Linearly Scheduled Array Processors
%A J. A.B. Fortes
%A D. I. Moldovan
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 224-231

%T Modular Matrix Multiplication on a Linear Array
%A I. V. Ramakrishnan
%A P. J. Varman
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 232-238

%T Joint Encryption and Error Correction Schemes
%A T. R.N. Rao
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 240-241

%T Unidirectional Error Correction/Detection for VLSI Memory
%A Bella Bose
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 242-244

%T Error-Correcting Codes for Semiconductor Memories
%A C. L. Chen
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 245-247

%T Soft Error Correction for Increased Densities in VLSI Memories
%A Khaled Abdel-Ghaffar
%A Robert J. McEliece
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 248-250

%T Combining Speed with Alpha-Particle Induced Memory Error Tolerance in a Large Boolean Vector Machine - Extended Abstract
%A Richard M. King
%A Robert A. Wagner
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 251-253

%T On the Performance of Loosely Coupled Multiprocessors
%A Laxmi N. Bhuyan
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 256-262

%T Scheduling of Tasks for Distributed Processors
%A Ravi Mehrotra
%A Sarosh N. Talukdar
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 263-270

%T Message Repository Definitional Facility: An Architectural Model for Interprocess Communication
%A Krishna M. Kavi
%A Edward W. Banios
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 271-278

%T Fault-Secure Algorithms for Multiple-Processor Systems
%A Prithviraj Banerjee
%A Jacob A. Abraham
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 279-287

%T Execution of Logic Programs on a Dataflow Architecture
%A Lubomir Bic
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 290-296

%T A High Performance Factoring Machine 
%A W. G. Rudd
%A Duncan A. Buell
%A Donald M. Chiarulli
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 297-300

%T A Characterization of Processor Performance in the VAX-11/780
%A Joel S. Emer
%A Douglas W. Clark
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 301-310

%T The Peripheral Processor PP4 - A Highly Regular VLSI Processor
%A W. D. Moeller
%A G. Sandweg
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 312-318

%T VLSI Based Design Principles for MIMD Multiprocessor Computers with Distributed Memory Management
%A Lars Philipson
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 319-327

%T A Multiprocessor Network Suitable for Single-Chip VLSI Implementation
%A M. R. Samatham
%A D. K. Pradhan
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 328-337

%T Dynamic Decentralized Cache Schemes for MIMD Parallel Processors
%A Larry Rudolph
%A Zary Segall
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 340-347

%T A Low-Overhead Coherence Solution for Multiprocessors with Private Cache Memories
%A Mark S. Papamarcos
%A Janak H. Patel
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 348-354

%T An Economical Solution to the Cache Coherence Problem
%A James Archibald
%A Jean-Loup Baer
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 355-362 

%T Cache Hit Ratios With Geometric Task Switch Intervals
%A Ilkka J. Haikala
%J Proc. 11th Annual Symposium on Computer Architecture
%D June 1984
%P 364-371